AT24C128 Datasheet, PDF (4/15 Pages) ATMEL Corporation – 2-Wire Serial EEPROMs

AC Characteristics
Applicable over recommended operating range from T_A = -40°C to +85°C, V_CC = +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
Symbol
f_SCL
t_LOW
t_HIGH
t_AA
t_BUF
t_HD.STA
t_SU.STA
t_HD.DAT
t_SU.DAT
t_R
t_F
t_SU.STO
t_DH
t_WR
Endurance⁽¹⁾
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can start⁽¹⁾
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time⁽¹⁾
Inputs Fall Time⁽¹⁾
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
1.8-volt
Min
Max
100
4.7
4.0
0.1
4.5
4.7
4.0
4.7
0
200
1.0
300
4.7
100
20
100K
Notes:
1. This parameter is characterized and is not 100% tested.
2. AC measurement conditions:
R_L (connects to V_CC): 1.3KΩ (2.7V, 5V), 10KΩ (1.8V)
Input pulse voltages: 0.3V_CC to 0.7V_CC
Input rise and fall times: ≤50ns
Input and output timing reference voltages: 0.5V_CC
2.7-volt
Min
Max
400
1.3
1.0
0.05
0.9
1.3
0.6
0.6
0
100
0.3
300
0.6
50
10
100K
5.0-volt
Min
Max
1000
0.6
0.4
0.05 0.55
Units
kHz
µs
µs
µs
0.5
µs
0.25
0.25
0
100
0.25
50
100K
µs
µs
µs
ns
0.3
µs
100
ns
µs
ns
10
ms
Write
Cycles
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is nor-
mally pulled high with an external device. Data on the SDA
pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL
high periods will indicate a start or stop condition as defined
below.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing dia-
gram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are seri-
ally transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C128/256 features a low
power standby mode which is enabled: a) upon power-up
and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power
loss or system reset, any 2-wire part can be reset by follow-
ing these steps: (a) Clock up to 9 cycles, (b) look for SDA
high in each cycle while SCL is high and then (c) create a
start condition as SDA is high.
4
AT24C128/256