AT17LV512A-10PU Datasheet, PDF (4/18 Pages) ATMEL Corporation – FPGA Configuration EEPROM Memory

3. Device Description
The control signals for the configuration EEPROM (nCS, RESET/OE and DCLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire configura-
tion process and retrieve data from the configuration EEPROM without requiring an external
controller.
The configuration EEPROM’s RESET/OE and nCS pins control the tri-state buffer on the DATA
output pin and enable the address counter and the oscillator. When RESET/OE is driven Low,
the configuration EEPROM resets its address counter and tri-states its DATA pin. The nCS pin
also controls the output of the AT17A series configurator. If nCS is held High after the
RESET/OE pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is
driven subsequently Low, the counter and the DATA output pin are enabled. When RESET/OE
is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regard-
less of the state of the nCS.
When the configurator has driven out all of its data and nCASC is driven Low, the device tri-
states the DATA pin to avoid contention with other configurators. Upon power-up, the address
counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High,
this document will describe RESET/OE.
4. Pin Description
AT17LV65A/
AT17LV128A/
AT17LV256A
AT17LV512A/
AT17LV010A
Name
20
I/O
PLCC
8
PDIP
20
PLCC
DATA
I/O
2
1
2
DCLK
I
4
2
4
WP1
I
–
–
5
RESET/OE
I
8
3
8
nCS
I
9
4
9
GND
10
5
10
nCASC
O
12
6
12
A2
I
READY
O
–
–
15
SER_EN
I
18
7
18
V_CC
20
8
20
Note: 1. The nCASC feature is not available on the AT17LV65A device.
32
TQFP
31
2
4
7
10
12
15
20
23
27
AT17LV002A
20
PLCC
32
TQFP
2
31
4
2
5
4
8
7
9
10
10
12
12
15
15
20
18
23
20
27
4 AT17LV65A/128A/256A/512A/002A
2322G–CNFG–03/06