AT90USB646_14 Datasheet, PDF (399/456 Pages) ATMEL Corporation – USB boot loader programmed by default in the factory

AT90USB64/128
31.10 External data memory timing
Table 31-6. External data memory characteristics, 4.5 - 5.5 Volts, no wait-state.
8MHz oscillator
Variable oscillator
Symbol Parameter
Min.
Max.
Min.
Max.
0
1/t_CLCL
1
t_LHLL
2
t_AVLL
3a t_{LLAX_ST}
Oscillator Frequency
ALE Pulse Width
Address Valid A to ALE Low
Address Hold After ALE Low,
write access
115
57.5
5
0.0
16
1.0t_CLCL-10
0.5t_CLCL-5 ⁽¹⁾
5
3b t_{LLAX_LD}
4
t_AVLLC
5
t_AVRL
6
t_AVWL
7
t_LLWL
8
t_LLRL
9
t_DVRH
10 t_RLDV
11 t_RHDX
12 t_RLRH
13 t_DVWL
14 t_WHDX
15 t_DVWH
16 t_WLWH
Address Hold after ALE Low,
read access
Address Valid C to ALE Low
Address Valid to RD Low
Address Valid to WR Low
ALE Low to WR Low
ALE Low to RD Low
Data Setup to RD High
Read Low to Data Valid
Data Hold After RD High
RD Pulse Width
Data Setup to WR Low
Data Hold After WR High
Data Valid to WR High
WR Pulse Width
5
57.5
115
115
47.5
47.5
40
0
115
42.5
115
125
115
67.5
67.5
75
5
0.5t_CLCL-5 ⁽¹⁾
1.0t_CLCL-10
1.0t_CLCL-10
0.5t_CLCL-15 ⁽²⁾
0.5t_CLCL-15 ⁽²⁾
40
0
1.0t_CLCL-10
0.5t_CLCL-20 ⁽¹⁾
1.0t_CLCL-10
1.0t_CLCL
1.0t_CLCL-10
0.5t_CLCL+5 ⁽²⁾
0.5t_CLCL+5 ⁽²⁾
1.0t_CLCL-50
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
Unit
MHz
ns
Table 31-7. External data memory characteristics, 4.5 - 5.5 Volts, 1 cycle wait-state.
8MHz oscillator
Variable oscillator
Symbol Parameter
Min.
Max.
Min.
Max.
0 1/t_CLCL
10 t_RLDV
12 t_RLRH
15 t_DVWH
16 t_WLWH
Oscillator Frequency
Read Low to Data Valid
RD Pulse Width
Data Valid to WR High
WR Pulse Width
0.0
16
200
2.0t_CLCL-50
240
2.0t_CLCL-10
240
2.0t_CLCL
240
2.0t_CLCL-10
Unit
MHz
ns
7593L–AVR–09/12
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