ATTINY87_10 Datasheet, PDF (39/292 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 8K/16K Bytes In-System Programmable Flash and LIN Controller

ATtiny87/ATtiny167
Table 4-10.
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Clock Prescaler Select
CLKPS2
CLKPS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock Division Factor
1
2
4
8
16
32
64
128
256
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
4.5.3
CLKCSR – Clock Control & Status Register
Bit
7
6
(0x62)
CLKCCE
–
Read/Write
R/W
R
Initial Value
0
0
5
4
3
2
1
0
–
CLKRDY CLKC3 CLKC2 CLKC1 CLKC0 CLKCSR
R
R
R/W
R/W
R/W
R/W
0
0
0
0
0
0
• Bit 7 – CLKCCE: Clock Control Change Enable
The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The
CLKCCE bit is only updated when the other bits in CLKCSR are simultaneously written to
zero. CLKCCE is cleared by hardware four cycles after it is written or when the CLKCSR bits
are written. Rewriting the CLKCCE bit within this time-out period does neither extend the
time-out period, nor clear the CLKCCE bit.
• Bits 6:5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny87/167 and will always read as zero.
• Bit 4 – CLKRDY: Clock Ready Flag
This flag is the output of the ‘Clock Availability ’ logic.
This flag is cleared by the ‘Request for Clock Availability’ command or ‘Enable Clock Source’
command being entered.
It is set when ‘Clock Availability’ logic confirms that the (selected) clock is running and is sta-
ble. The delay from the request and the flag setting is not fixed, it depends on the clock
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