AT86RF233_14 Datasheet, PDF (39/225 Pages) ATMEL Corporation – Low Power, 2.4GHz Transceiver for ZigBee, RF4CE, IEEE

7.1.2.4 DEEP_SLEEP – Deep Sleep State
In DEEP_SLEEP state, the entire radio transceiver is disabled. No circuitry is operating
beyond the circuitry monitoring pin 11 (SLP_TR). The radio transceiver current
consumption is reduced to leakage current only. This state can only be entered from
state PREP_DEEP_SLEEP, by setting the SLP_TR = H.
Setting SLP_TR = L returns the radio transceiver back to the TRX_OFF state. After
DEEP_SLEEP state the radio transceiver register contents and the AES register
contents obtain the reset values while the contents of the Frame Buffer are lost. The
CLKM starts with the default 1MHz master clock at pin 17 (CLKM) after the crystal
oscillator has stabilized.
All Atmel AT86RF233 digital inputs are pulled-up or pulled-down during DEEP_SLEEP
state, refer to Section 1.3.2, except SLP_TR.
7.1.2.5 TRX_OFF – Clock State
In TRX_OFF the crystal oscillator is running and the master clock is available if
enabled. The SPI interface and digital voltage regulator are enabled, thus the radio
transceiver registers, the Frame Buffer and security engine (AES) are accessible (see
Section 9.3 and Section 11.1).
In contrast to P_ON state the pull-up and pull-down configuration is disabled.
Notes: 1. Pin 11 (SLP_TR) and pin 8 (/RST) are available for state control.
2. The analog front-end is disabled during TRX_OFF state.
Entering the TRX_OFF state from P_ON, SLEEP, DEEP_SLEEP or RESET state is
indicated by interrupt IRQ_4 (AWAKE_END) if enabled.
7.1.2.6 PLL_ON – PLL State
Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator
(AVREG) first. After the voltage regulator has been settled (see Table 7-2), the PLL
frequency synthesizer is enabled. When the PLL has been settled at the receive
frequency to a channel defined by register bits CHANNEL (register 0x08,
PHY_CC_CCA) or register bits CC_NUMBER (register 0x13, CC_CTRL_0) and
CC_BAND (register 0x14, CC_CTRL_1), refer to Section 9.7.2, a successful PLL lock is
indicated by issuing an interrupt IRQ_0 (PLL_LOCK).
If an RX_ON command is issued in PLL_ON state, the receiver is enabled immediately.
If the PLL has not been settled before the state change nevertheless takes place. Even
if the register bits TRX_STATUS (register 0x01, TRX_STATUS) indicates RX_ON,
actual frame reception can only start once the PLL has locked.
The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4.
7.1.2.7 RX_ON and BUSY_RX – RX Listen and Receive State
In RX_ON state the receiver is in the RX data polling mode and the PLL frequency
synthesizer is locked to its preprogrammed frequency.
The Atmel AT86RF233 receive mode is internally separated into RX_ON state and
BUSY_RX state. There is no difference between these states with respect to the analog
radio transceiver circuitry, which are always turned on. In both states, the receiver and
the PLL frequency synthesizer are enabled.
During RX_ON state, the receiver listens for incoming frames. After detecting a valid
synchronization header (SHR), the Atmel AT86RF233 automatically enters the
BUSY_RX state. The reception of a valid PHY header (PHR) generates an
IRQ_2 (RX_START) if enabled.
MCU Wireless AT86RF233 [PRELIMINARY DATASHEET] ³⁹
Atmel-8351E-MCU_Wireless-AT86RF233_Datasheet_072014