AT32UC3A3256S_09 Datasheet, PDF (39/75 Pages) ATMEL Corporation – AVR32 32-Bit Microcontroller

AT32UC3A3
• Compatible with PMBus
• Compatible with Atmel Two-Wire Interface Serial Memories
• DMA interface for reducing CPU load
• Arbitrary transfer lengths, including 0 data bytes
• Optional clock stretching if transmit or receive buffers not ready for data transfer
8.4.16
Synchronous Serial Controller
• Provides serial synchronous communication links used in audio and telecom applications
• Independent receiver and transmitter, common clock divider
• Interfaced with two Peripheral DMA Controller channels to reduce processor overhead
• Configurable frame sync and data length
• Receiver and transmitter can be configured to start automatically or on detection of different
events on the frame sync signal
• Receiver and transmitter include a data signal, a clock signa,l and a frame synchronization signal
8.4.17
Universal Synchronous Asynchronous Receiver Transmitter
• Programmable Baud Rate Generator
• 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications
– 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode
– Parity Generation and Error Detection
– Framing Error Detection, Overrun Error Detection
– MSB- or LSB-first
– Optional Break Generation and Detection
– By 8 or by 16 Over-sampling Receiver Frequency
– Optional Hardware Handshaking RTS-CTS
– Optional Modem Signal Management DTR-DSR-DCD-RI
– Receiver Time-out and Transmitter Timeguard
– Optional Multidrop Mode with Address Generation and Detection
• RS485 with Driver Control Signal
• ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
– NACK Handling, Error Counter with Repetition and Iteration Limit
• IrDA Modulation and Demodulation
– Communication at up to 115.2 Kbps
• SPI Mode
– Master or Slave
– Serial Clock Programmable Phase and Polarity
– SPI Serial Clock (CLK) Frequency up to Internal Clock Frequency CLK_USART/4
• LIN Mode
– Compliant with LIN 1.3 and LIN 2.0 specifications
– Master or Slave
– Processing of frames with up to 256 data bytes
– Response Data length can be configurable or defined automatically by the Identifier
– Self synchronization in Slave node configuration
– Automatic processing and verification of the “Synch Break” and the “Synch Field”
– The “Synch Break” is detected even if it is partially superimposed with a data byte
– Automatic Identifier parity calculation/sending and verification
– Parity sending and verification can be disabled
– Automatic Checksum calculation/sending and verification
– Checksum sending and verification can be disabled
– Support both “Classic” and “Enhanced” checksum types
39
32072AS–AVR32–03/09