AT89C5130A-M Datasheet, PDF (38/184 Pages) ATMEL Corporation – 8-bit Flash Microcontroller with Full Speed USB Device

Flash Registers and
Memory Map
Hardware Registers
Bootloader Jump Bit (BLJB)
Flash Memory Lock Bits
The AT89C5130A/31A-M Flash memory uses several registers:
• Hardware registers can only be accessed through the parallel programming modes
which are handled by the parallel programmer.
• Software registers are in a special page of the Flash memory which can be
accessed through the API or with the parallel programming modes. This page,
called “Extra Flash Memory”, is not in the internal Flash program memory
addressing space.
The only hardware registers of the AT89C5130A/31A-M is called Hardware Security
Byte (HSB).
Table 39. Hardware Security Byte (HSB)
7
6
5
4
3
2
1
0
X2
BLJB
OSCON1 OSCON0
-
LB2
LB1
LB0
Bit
Bit
Number Mnemonic Description
X2 Mode
7
X2
Cleared to force X2 mode (6 clocks per instruction)
Set to force X1 mode, Standard Mode (Default).
Bootloader Jump Bit
6
BLJB Set this bit to start the user’s application on next reset at address 0000h.
Cleared this bit to start the bootloader at address F400h (default).
Oscillator Control Bits
These two bits are used to control the oscillator in order to reduce consumption.
OSCONOSCON0Description
5-4
OSCON1-0 _{1 1 The oscillator is configured to run from 0 to 32 MHz}
1 0 The oscillator is configured to run from 0 to 16 MHz
0 1 The oscillator is configured to run from 0 to 8 MHz
0 0 This configuration shouldn’t be set
3
-
Reserved
User Memory Lock Bits
2-0
LB2-0
See Table 40
One bit of the HSB, the BLJB bit, is used to force the boot address:
• When this bit is set the boot address is 0000h.
• When this bit is reset the boot address is F400h. By default, this bit is cleared and
the ISP is enabled.
The three lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 40.
38 AT89C5130A/31A-M
4337C–USB–02/05