SAMD20J Datasheet, PDF (370/586 Pages) ATMEL Corporation – ARM-Based Embedded Flash Microcontroller

26.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
26.5.1 I/O Lines
Using the SERCOM’s I/O lines requires the I/O pins to be configured using port configuration (PORT). Refer to “PORT”
on page 289 for details.
When the SERCOM is configured for SPI operation, the pins should be configured according to Table 26-1. If the
receiver is disabled, the data input pin can be used for other purposes. In master mode the slave select line (_SS) is
controlled by software.
Table 26-1. SPI Pin Configuration
Pin
MOSI
MISO
SCK
_SS
Master SPI
Output
Input
Output
User defined output enable
Slave SPI
Input
Output
Input
Input
The combined configuration of PORT and the Data In/Data Out and Data Out Pinout bit groups in Control A register will
define the physical position of the SPI signals in Table 26-1.
26.5.2 Power Management
The SPI can continue to operate in any sleep mode. The SPI interrupts can be used to wake up the device from sleep
modes. Refer to “PM – Power Manager” on page 105 for details on the different sleep modes.
26.5.3 Clocks
The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Power Manager, and the default
state of CLK_SERCOMx_APB can be found in the Peripheral Clock Masking section in the “PM – Power Manager” on
page 105.
A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured and enabled in
the Generic Clock Controller before using the SPI. Refer to “GCLK – Generic Clock Controller” on page 83 for details.
This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to “Synchronization” on page 377 for further
details.
26.5.4 DMA
Not applicable.
26.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the SPI, interrupts requires the Interrupt
Controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 28 for details.
26.5.6 Events
Not applicable.
Atmel SAM D20 [Preliminary DATASHEET] 370
42129A–SAM–06/2013