AT90CAN64_14 Datasheet, PDF (370/428 Pages) ATMEL Corporation – High-performance, Low-power AVR 8-bit Microcontroller

2. Required only for f_SCL > 100 kHz.
3. C_b = capacitance of one bus line in pF.
4. f_CK = CPU clock frequency
5. This requirement applies to all AT90CAN32/64/128 Two-wire Serial Interface operation. Other devices connected to the
Two-wire Serial Bus need only obey the general f_SCL requirement.
6. The actual low period generated by the AT90CAN32/64/128 Two-wire Serial Interface is (1/f_SCL - 2/f_CK), thus f_CK must be
greater than 6 MHz for the low time requirement to be strictly met at f_SCL = 100 kHz.
7. The actual low period generated by the AT90CAN32/64/128 Two-wire Serial Interface is (1/f_SCL - 2/f_CK), thus the low time
requirement will not be strictly met for f_SCL > 308 kHz when f_CK = 8 MHz. Still, AT90CAN32/64/128 devices connected to the
bus may communicate at full speed (400 kHz) with other AT90CAN32/64/128 devices, as well as any other device with a
proper t_LOW acceptance margin.
Figure 26-3. Two-wire Serial Bus Timing
SCL
SDA
t_SU;STA
t_of
t_LOW
t_HD;STA
t_HIGH
t_HD;DAT
t_LOW
t_SU;DAT
t_r
t_SU;STO
t_BUF
26.6 SPI Timing Characteristics
See Figure 26-4 and Figure 26-5 for details.
Table 26-4. SPI Timing Parameters
Description
Mode
1
SCK period
Master
2
SCK high/low
Master
3
Rise/Fall time
Master
4
Setup
Master
5
Hold
Master
6
Out to SCK
Master
7
SCK to out
Master
8
SCK to out high
Master
9
SS low to out
Slave
10
SCK period
11
SCK high/low ⁽¹⁾
12
Rise/Fall time
Slave
Slave
Slave
Min.
4 • t_ck
2 • t_ck
Typ.
See Table 16-4
50% duty cycle
3.6
10
10
0.5 • t_sck
10
10
15
Max.
ns
1.6 µs
370 AT90CAN32/64/128
7679H–CAN–08/08