AT83C5111_14 Datasheet, PDF (37/86 Pages) ATMEL Corporation – 10-bit, 8 Channels A/D Converter

Figure 3. Full-Duplex Master-slave Interconnection
8-bit Shift register
SPI
Clock Generator
Master MCU
MISO
MOSI
SCK
SS _VDD
MISO
MOSI
SCK
SS
VSS
8-bit Shift register
Slave MCU
Master Mode
The SPI operates in Master mode. Only one Master SPI device can initiate transmis-
sions. Software begins the transmission from a Master SPI module by writing to the
Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is imme-
diately transferred to the shift register. The byte begins shifting out on MOSI pin under
the control of the serial clock, SCK. Simultaneously, another byte shifts in from the
Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral
transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes
set, the received byte from the Slave is transferred to the receive data register in
SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA)
with the SPIF bit set, and then reading the SPDAT.
When the pin SS is pulled down during a transmission, the data is interrupted and when
the transmission is established again, the data present in the SPDAT is present.
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity
using two bits in the SPCON: the Clock POLarity (CPOL ⁽¹⁾) and the Clock PHAse
(CPHA⁽¹⁾). CPOL defines the default SCK line level in idle state. It has no significant
effect on the transmission format. CPHA defines the edges on which the input data are
sampled and the edges on which the output data are shifted (Figure 15 and Figure 16).
The clock phase and polarity should be identical for the Master SPI device and the com-
municating Slave device.
Figure 4. Data Transmission Format (CPHA = 0)
SCK Cycle Number
1
2
3
4
5
6
7
8
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI (from Master)
MISO (from Slave)
SS (to Slave)
Capture Point
MSB
bit6
bit5
bit4
bit3
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
bit2
bit1
LSB
1.
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).
37 AT8xC5111
4190B–8051–02/08