ATTINY11 Datasheet, PDF (36/91 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 1K Byte Flash

Watchdog Timer
The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the
Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in
Table 16. See characterization data for typical values at other V_CC levels. The WDR –
Watchdog Reset – instruction resets the Watchdog Timer. Eight different clock cycle
periods can be selected to determine the reset period. If the reset period expires without
another Watchdog reset, the ATtiny11/12 resets and executes from the reset vector. For
timing details on the Watchdog reset, refer to page 23.
To prevent unintentional disabling of the watchdog, a special turn-off sequence must be
followed when the watchdog is disabled. Refer to the description of the Watchdog Timer
Control Register for details.
Figure 25. Watchdog Timer
Oscillator
1 MHz at V_CC = 5V
350 kHz at V_CC = 3V
110 kHz at V_CC = 2V
Watchdog Timer Control
Register – WDTCR
Bit
7
6
5
4
3
2
1
0
$21
-
-
-
WDTOE
WDE
WDP2
WDP1
WDP0
WDTCR
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 7..5 - Res: Reserved Bits
These bits are reserved bits in the ATtiny11/12 and will always read as zero.
• Bit 4 - WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not
be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to
the description of the WDE bit for a watchdog disable procedure.
• Bit 3 - WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared
(zero) the Watchdog Timer function is disabled. WDE can be cleared only when the
WDTOE bit is set(one). To disable an enabled watchdog timer, the following procedure
must be followed:
36 ATtiny11/12
1006D–AVR–07/03