ATMEGA16_14 Datasheet, PDF (353/357 Pages) ATMEL Corporation – High Endurance Non-volatile Memory segments

Prescaling and Conversion Timing 207
Changing Channel or Reference Selection 210
ADC Noise Canceler 211
ADC Conversion Result 216
JTAG Interface and On-chip Debug System 222
Features 222
Overview 222
Test Access Port – TAP 222
TAP Controller 224
Using the Boundary-scan Chain 225
Using the On-chip Debug System 225
On-chip Debug Specific JTAG Instructions 226
On-chip Debug Related Register in I/O Memory 227
Using the JTAG Programming Capabilities 227
Bibliography 227
IEEE 1149.1 (JTAG) Boundary-scan 228
Features 228
System Overview 228
Data Registers 228
Boundary-scan Specific JTAG Instructions 230
Boundary-scan Chain 232
ATmega16 Boundary-scan Order 241
Boundary-scan Description Language Files 245
Boot Loader Support – Read-While-Write Self-Programming 246
Features 246
Application and Boot Loader Flash Sections 246
Read-While-Write and no Read-While-Write Flash Sections 246
Boot Loader Lock Bits 248
Entering the Boot Loader Program 249
Addressing the Flash during Self-Programming 251
Self-Programming the Flash 252
Memory Programming 259
Program And Data Memory Lock Bits 259
Fuse Bits 260
Signature Bytes 261
Calibration Byte 261
Page Size 262
Parallel Programming Parameters, Pin Mapping, and Commands 262
Parallel Programming 265
Serial Downloading 273
Programming via the JTAG Interface 278
iv ATmega16(L)
2466T–AVR–07/10