ATAR092-D Datasheet, PDF (34/96 Pages) ATMEL Corporation – Low-current Microcontroller for Wireless Communication

Figure 30. Timer 2
For 12-bit compare data value:
For 8-bit compare data value:
For 4-bit compare data value:
m=x+1
n=y+1
l=z+1
0 ≤x ≤4095
0 ≤y ≤255
0 ≤z ≤15
I/O-bus
P4CR
T2M1
T2I
T2M2
SYSCL
T1OUT
TOG3
SCL
CL2/1
4-bit Counter 2/1
CL2/2
RES
OVF1 POUT
DCG
T2C
Compare 2/1
Control
CM1
T2CO1
SSI POUT
T2CM
I/O-bus
DCGO
8-bit Counter 2/2
RES
OVF2
TOG2
Compare 2/2
INT4
T2CO2
T2O
OUTPUT
MOUT
M2
to
Modulator 3
Bi-phase
Manchester
modulator
Timer 2
modulator
output-stage
SO
Control
SSI
SSI
Timer 2 Modes
Mode 1: 12-bit Compare Counter
The 4-bit stage and the 8-bit stage work together as a 12-bit compare counter. A com-
pare match signal of the 4-bit and the 8-bit stage generates the signal for the counter
reset, toggle flip-flop or interrupt. The compare action is programmable via the compare
mode register (T2CM). The 4-bit counter overflow (OVF1) supplies the clock output
(POUT) with clocks. The duty cycle generator (DCG) has to be bypassed in this mode.
Figure 31. 12-bit Compare Counter
CL2/1
4-bit counter
RES
POUT (CL2/1 /16)
DCG
8-bit counter
OVF2
RES
4-bit compare
CM1
CM2
8-bit compare
4-bit register
T2D1, 0
8-bit register
T2RM
T2OTM
Timer 2
output mode
and T2OTM-bit
T2IM
T2CTM
TOG2
INT4
34 ATAR092-D
4594C–4BMCU–12/04