AT87C51RB2_14 Datasheet, PDF (34/86 Pages) ATMEL Corporation – Programmable Clock Out and Up/Down Timer/Counter 2

6.4 TS80C51Rx2 Serial I/O Port
The serial I/O port in the TS80C51Rx2 is compatible with the serial I/O port in the 80C52.
It provides both synchronous and asynchronous communication modes. It operates as an Uni-
versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2
and 3). Asynchronous transmission and reception can occur simultaneously and at different
baud rates
Serial I/O port includes the following enhancements:
• Framing error detection
• Automatic address recognition
6.4.1
Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 6-
10).
Figure 6-10. Framing Error Block Diagram
SM0/FE SM1 SM2 REN TB8 RB8 TI
RI SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD = 0)
SMOD1SMOD0 -
POF GF1 GF0 PD IDL
To UART framing error control
PCON (87h)
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
6-14.) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only soft-
ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 6-
11 and Figure 6-12).
Figure 6-11. UART Timings in Mode 1
RXD
D0 D1 D2 D3 D4 D5 D6 D7
RI
SMOD0=X
Start
bit
Data byte
Stop
bit
FE
SMOD0=1
34 AT/TS8xC51Rx2
4188F–8051–01/08