AT25DF161 Datasheet, PDF (34/60 Pages) ATMEL Corporation – 16-Megabit 2.7-volt Minimum SPI Serial Flash Memory

10.5
Read OTP Security Register
The OTP Security Register can be sequentially read in a similar fashion to the Read Array oper-
ation up to the maximum clock frequency specified by f_MAX. To read the OTP Security Register,
the CS pin must first be asserted and the opcode of 77h must be clocked into the device. After
the opcode has been clocked in, the three address bytes must be clocked in to specify the start-
ing address location of the first byte to read within the OTP Security Register. Following the
three address bytes, two dummy bytes must be clocked into the device before data can be
output.
After the three address bytes and the dummy bytes have been clocked in, additional clock
cycles will result in OTP Security Register data being output on the SO pin. When the last byte
(00007Fh) of the OTP Security Register has been read, the device will continue reading back at
the beginning of the register (000000h). No delays will be incurred when wrapping around from
the end of the register to the beginning of the register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
Figure 10-5. Read OTP Security Register
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36
OPCODE
ADDRESS BITS A23-A0
DON'T CARE
0 1 1 1 0 1 1 1AAAAAA
MSB
MSB
HIGH-IMPEDANCE
AAAXXXXXX
MSB
XXX
DATA BYTE 1
DDDDDDDDDD
MSB
MSB
34 AT25DF161 [Preliminary]
3687C–DFLASH–7/09