TS68882 Datasheet, PDF (33/43 Pages) ATMEL Corporation – CMOS Enhanced Floating-point Co-processor

TS68882
Table 12 indicates that all accesses over a 32-bit bus where A4 equals zero are to 16-bit
registers. The TS68882 implements all 16-bit co-processor interface registers on data
lines D16 - D13 (to eliminate the need for on-chip multiplexers); however, the
TS68020/TS68030 expects 16-bit registers that are located in a 32-bit port at odd word
addresses (A1 = 1) to be implemented on data lines D0-D15. For accesses to these reg-
isters when configured for 32-bit bus operation, the TS68882 generates DSACK signals
as listed in Table 12 to inform the TS68020/TS68030 of valid data on D16 - D31 instead
of D0-D15.
An external holding resistor is required to maintain both DSACK0 and DSACK1 high
between bus cycles. In order to reduce the signal rise time, the DSACK0 and DSACK1
lines are actively pulled up (negated) by the TS68882 following the rising edge of AS or
DS and both DSACK lines are then three-stated (placed in the high-impedance state) to
avoid interference with the next bus cycle.
Table 12. DSACK Assertions
Data Bus
A4
DSACK1
32-bit
1
L
32-bit
0
L
16-bit
x
L
8-bit
x
H
All
x
H
DSACK2
L
H
H
L
H
Comments
Valid data on D31-D0
Valid data on D31-D16
Valid data on D31-D16 or D15-D0
Valid data on D31-D24, D23-D16, D15-D8, D7-D0
Insert Wait States in Current Bus Cycle
Reset (RESET)
This active-low input signal causes the TS68882 to initialize the floating-point data regis-
ters to non-signaling not-a-numbers (NANs) and clears the floating-point control, status,
and instruction address registers.
When performing a power-up reset, external circuitry should keep the RESET line
asserted to a minimum of four clock cycles after V_CC is within tolerance. This assures
correct initialization of the TS68882 when power is applied. For compatibility with all
TS68000 Family devices, 100 milliseconds should be used as the minimum.
When performing a reset of the TS68882 after V_CC has been within tolerance for more
than the initial power-up time, the RESET line must have an asserted pulse width which
is greater than two clock cycles. For compatibility with all TS68000 Family devices, 10
clock cycles should be used as the minimum.
Clock (CLK)
The TS68882 clock input is a TTL-compatible signal that is internally buffered for devel-
opment of the internal clock signals. The clock input should be a constant frequency
square wave with no stretching or shaping techniques required. The clock should not be
gated off at any time and must conform to minimum and maximum period and pulse
width times.
Sense Device (SENSE)
This pin may be used optionally as an additional GND pin, or as an indicator to external
hardware that the TS68882 is present in the system. This signal is internally connected
to the GND of the die, but it is not necessary to connect it to the external ground for cor-
rect device operation. If a pullup resistor (which should be larger than 10 kΩ) is
connected to this pin location, external hardware may sense the presence of the
TS688882 in a system.
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2119A–HIREL–04/02