ATTINY5_14 Datasheet, PDF (32/170 Pages) ATMEL Corporation – Atmel 8-bit AVR Microcontroller

8.4 Register Description
8.4.1
WDTCSR – Watchdog Timer Control and Status Register
Bit
7
6
5
4
0x31
WDIF
WDIE
WDP3
–
Read/Write
R/W
R/W
R/W
R
Initial Value
0
0
0
0
3
WDE
R/W
X
2
WDP2
R/W
0
1
WDP1
R/W
0
0
WDP0
R/W
0
WDTCSR
• Bit 7 – WDIF: Watchdog Timer Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt.
WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is
cleared by writing a logic one to the flag. When the WDIE is set, the Watchdog Time-out Interrupt is requested.
• Bit 6 – WDIE: Watchdog Timer Interrupt Enable
When this bit is written to one, the Watchdog interrupt request is enabled. If WDE is cleared in combination with
this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is requested if time-out in the
Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog
Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hard-
ware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while
using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This
should however not be done within the interrupt service routine itself, as this might compromise the safety-function
of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will
be applied.
Table 8-2.
WDTON⁽¹⁾
1
1
1
1
0
Watchdog Timer Configuration
WDE
WDIE Mode
0
0
Stopped
0
1
Interrupt Mode
1
0
System Reset Mode
1
1
Interrupt and System
Reset Mode
x
x
System Reset Mode
Action on Time-out
None
Interrupt
Reset
Interrupt, then go to
System Reset Mode
Reset
Note: 1. WDTON configuration bit set to “0“ means programmed and “1“ means unprogrammed.
• Bit 4 – Res: Reserved Bit
This bit is reserved and will always read zero.
• Bit 3 – WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in RSTFLR. This means that WDE is always set when WDRF is set. To clear WDE,
WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe
start-up after the failure.
ATtiny4/5/9/10 [DATASHEET] 32
8127F–AVR–02/2013