ATTINY15L_14 Datasheet, PDF (32/85 Pages) ATMEL Corporation – Advanced RISC Architecture

Figure 22. Effects of Unsynchronized OCR Latching
Compare Value Changes
Counter Value
Compare Value
Synchronized OC1A Latch
PWM Output OC1A
Compare Value Changes
Counter Value
Compare Value
Unsynchronized OC1A Latch
Glitch
PWM Output OC1A
During the time between the write and the latch operation, a read from OCR1A will read
the contents of the temporary location. This means that the most recently written value
always will read out of OCR1A.
When OCR1A contains $00 or the top value, as specified in OCR1B Register, the output
PB1(OC1A) is held low or high according to the settings of COM1A1/COM1A0. This is
shown in Table 13.
Timer/Counter1 Output
Compare RegisterB – OCR1B
Bit
7
6
5
4
3
2
1
0
$2D
MSB
LSB
OCR1B
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
The Output Compare Register1 (OCR1B) is an 8-bit read/write register. This register is
used in the PWM mode only, and it limits the top value to which the Timer/Counter1
keeps counting. After reaching OCR1B in PWM mode, the counter starts from $00.
Table 13. PWM Outputs when OCR1A = $00 or OCR1B
COM1A1
COM1A0
OCR1B
1
0
$00
1
0
OCR1B
1
1
$00
1
1
OCR1B
Output PWMn
L
H
H
L
In PWM mode, the Timer Overflow Flag (TOV1) is set as in normal Timer/Counter
mode. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode,
i.e., it is executed when TOV1 is set provided that Timer Overflow Interrupt and global
interrupts are enabled. This also applies to the Timer Output Compare A Flag and
interrupt.
32 ATtiny15L
1187H–AVR–09/07