ATAR092-D_14 Datasheet, PDF (31/96 Pages) ATMEL Corporation – Up to 7 External/Internal Interrupt Sources

ATAR092-D
Figure 29. Timer 1 and Watchdog
T1C1 T1RM T1C2 T1C1 T1C0
Write of the
T1C1 register
3
Decoder
MUX for interval timer
RES ^{Q1 Q2 Q3 Q4 Q5}
Q8
Q11
CL1
CL
Q6
Q8
Q11
Decoder
2
WDC WDL WDR WDT1 WDT0
MUX for watchdog timer
RES
Watchdog
mode control
T1C2 T1BP T1IM
T1MUX
T1IM=0
INT2
Q14 _SUBCL
T1IM=1
T1OUT
Q14
Watchdog
Divider/8
WDCL
Divider
RESET
RESET
(NRST)
Read of the
CWD register
Timer 1 Control Register 1
(T1C1)
T1C1
Bit 3 Bit 2
T1RM T1C2
Bit 3 = MSB, Bit 0 = LSB
Bit 1
T1C1
Bit 0
T1C0
Address: '7'hex - Subaddress: '8'hex
Reset value: 1111b
T1RM
T1C2
T1C1
T1C0
Timer 1 Restart Mode T1RM = 0, write access without Timer 1 restart
T1RM = 1, write access with Timer 1 restart
Note: if WDL = 0, Timer 1 restart is impossible
Timer 1 Control bit 2
Timer 1 Control bit 1
Timer 1 Control bit 0
The three bits T1C[2:0] select the divider for timer 1. The resulting time interval depends
on this divider and the timer 1 input clock source. The timer input can be supplied by the
system clock, the 32 kHz oscillator or via clock management. If clock management gen-
erates the SUBCL, the selected input clock from the RC oscillator, 4 MHz oscillator or an
external clock is divided by 16.
31
4594C–4BMCU–12/04