ATSHA204A_14 Datasheet, PDF (30/82 Pages) ATMEL Corporation – Atmel CryptoAuthentication

6.2.1
Word Address Values
During a I²C write packet, the ATSHA204A interprets the second byte sent as the word address, which indicates
the packet function, as described in Table 6-2.
Table 6-2. Word Address Values
Name
Reset
Sleep
(Low Power)
Idle
Command
Reserved
Value
0x00
0x01
0x02
0x03
0x04 – 0xFF
Description
Reset the address counter. The next read or write transaction will start with the
beginning of the I/O buffer.
The ATSHA204A goes into the low-power sleep mode and ignores all subsequent I/O
transitions until the next Wake flag. The entire volatile state of the device is reset.
The ATSHA204A goes into the idle state and ignores all subsequent I/O transitions
until the next Wake flag. The contents of TempKey and RNG Seed registers are
retained.
Write subsequent bytes to sequential addresses in the input command buffer that
follow previous writes. This is the normal operation.
These addresses should not be sent to the device.
6.2.2
Command Completion Polling
After a complete command has been sent to the ATSHA204A, the device will be busy until the command
computation completes. The system has two options for this delay:
 Polling
The system should wait t_EXEC (typical) and then send a read sequence (See Section Section 6.3, “I²C
Transmission from the ATSHA204A Device”). If the device NACKs the device address, then it is still busy.
The system may delay for some time or immediately send another read sequence, again looping on NACK.
After a total delay of t_EXEC (max), the device will have completed the computation and return the results.
 Single Delay
The system should wait t_EXEC (max), after which the device will have completed execution and the result
can be read from the device using a normal read sequence.
6.3 I²C Transmission from the ATSHA204A Device
When the ATSHA204A is awake and not busy, the bus master can retrieve the current buffer contents from the
device using an I²C read. If valid command results are available, the size of the block returned is determined by
the particular command that has been run (See Section 8., “Security Commands”); otherwise, the size of the
block (and the first byte returned) will always be four: count, status/error, and 2-byte CRC. The bus timing is
shown in Figure 7-3.
Table 6-3. I²C transmission from ATSHA204A
ATSHA204A
Device
Address
I²C
Name
Direction
Device
To Slave
Address
Description
This byte selects a particular device on the I²C interface, and the
ATSHA204A will be selected if bits 1 thru 7 of this byte match bits 1 thru 7 of
the I2C_Address byte in the Configuration zone. Bit 0 of this byte is the
standard I²C R/W pin, and should be one to indicate that the bytes following
the device address travel from the slave to the master (read).
Data
Data_1,N
To Master
The output block, consisting of the count and status/error byte or the output
packet followed by the 2-byte CRC per Section 8.2.
30 ATSHA204A [DATASHEET]
Atmel-8885D-CryptoAuth-ATSHA204A-Datasheet_072014