U4223B Datasheet, PDF (3/18 Pages) ATMEL Corporation – Time-Code Receiver with A/D Converter

U4223B
Q1A, Q1B
SL
In order to achieve a high selectivity, a crystal is con-
nected between the Pins Q1A and Q1B. It is used with the
serial resonant frequency of the time-code transmitter
(e.g., 60 kHz WWVB, 77.5 kHz DCF or 40 kHz JG2AS).
The equivalent parallel capacitor of the filter crystal is
internally compensated. The compensated value is about
0.7 pF. If full sensitivity and selectivity are not needed,
the crystal filter can be substituted by a capacitor of 82 pF.
AGC hold mode: SL high (V_SL = V_CC) sets normal func-
tion, SL low (V_SL = 0) disconnects the rectifier and holds
the voltage V_INT at the integrator output and also the AGC
amplifier gain.
VCC
SL
Q1A
Q1B
GND
Figure 8.
Figure 5.
INT
REC
Rectifier output and integrator input: The capacitor C₁
between REC and INT is the lowpass filter of the rectifier
and at the same time a damping element of the gain
control.
Integrator output: The voltage V_INT is the control voltage
for the AGC. The capacitor C₂ between INT and DEC
defines the time constant of the integrator. The current
through the capacitor is the input signal of the decoder.
REC
Figure 6.
GND
INT
GND
Figure 9.
DEC
Decoder input: Senses the current through the integration
capacitor C₂. The dynamic input resistance has a value of
about 420 kW and is low compared to the impedance of
C₂.
FLA, FLB
Lowpass filter: A capacitor C₃ connected between FLA
and FLB suppresses higher frequencies at the trigger
circuit of the decoder.
DEC
Figure 7.
GND
FLB
Figure 10.
FLB
94 8377
Rev. A7, 06-Mar-01
3 (18)