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E1217X Datasheet, PDF (3/8 Pages) ATMEL Corporation – 32 KHZ STANDARD WATCH CMOS IC
e1217X
Functional Description
Voltage Regulator
Oscillator
Frequency Divider
Motor Drive Output
RESET
An integrated voltage regulator provides the oscillator with a well-controlled negative
supply voltage VREG. This improves the stability of the oscillator and keeps current con-
sumption at a minimum.
The oscillator inverter with feedback resistor generates the 32768 Hz clock frequency. A
total capacitance of 24 pF is integrated. This can be selected for COSCOUT in 2 pF
increments via a mask option.
A 21-bit binary counter is provided, dividing the oscillator frequency down to 1/64 Hz.
The leading six stages are connected to VDD and VREG, while the remaining 15 stages
are connected to VDD and VSS.
The e1217X contains two push-pull output buffers for driving bipolar stepping motors.
During a motor pulse, the n-channel device of one buffer and the p-channel device of
the other buffer are activated. The p-channel devices of both buffers are active (see Fig-
ure 3) between the two pulses.
Cycle time and pulse width can be chosen via a metal mask option (Table 1).
A debounced RESET input is provided. Connecting the RESET input to VDD resets the
12 low-order stages of the frequency divider, thus disabling further motor pulses. Motor
pulses, which are in progress when the reset function is applied, will be completed. After
releasing the RESET pad from VDD, the next motor pulse appears with a delay of one
half motor cycle on the drive output opposed to the former (Figure 4). Due to the
debounce circuitry on the RESET input, VDD must be applied for at least 31.2 ms. Dur-
ing RESET the input current is limited to 8 nA typically.
Test
A test frequency of 512 Hz is output to this pad which can be measured with a high
resistance probe (R ³ 10 MW, C ³ 20 pF). This signal can be used for testing and tuning
the oscillator. Connecting TEST to VDD for at least 4 ms changes the motor cycle time
from the selected value to the test cycle time (mask options), while the motor pulse
width remains unchanged (Figure 3).
This feature can be used to reduce the amount of time required for testing the mechani-
cal parts of the watch.
Table 1. Motor Options
Motor-cycle Parameters
Cycle time TM
Motor pulse width tM
Motor test cycle time TMT
Value
2, 4, 6, 8, 10, 12, 20, 24, 30, 40, 60, 80, 120 s
0.98 to 14.65 ms in increments of 0.98 ms
250, 125, 62.5 ms
3
4728A–CLOCK–06/03