ATA6620N_09 Datasheet, PDF (3/22 Pages) ATMEL Corporation – LIN Bus Transceiver with Integrated Voltage Regulator

ATA6620N
3. Functional Description
3.1 Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer),
all nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer
nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without
any restrictions.
3.2 Supply Pin (VS)
LIN operating voltage is V_S = 5V to 18V. After switching on V_S, the IC starts with the Pre-normal
mode and the voltage regulator is switched on (that is, 5V/50 mA output capability).
The supply current in Sleep mode is typically 10 µA and 40 µA in Silent mode.
3.3 Ground Pin (GND)
The IC is neutral on the LIN pin in case of GND disconnection. It is able to handle a ground shift
up to 3V for supply voltage above 9V at the VS pin.
3.4 Voltage Regulator Output Pin (VCC)
The internal 5V voltage regulator is capable of driving loads with up to 50 mA, supplying the
microcontroller and other ICs on the PCB. It is protected against overload by means of current
limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will
cause a reset signal at the NRES output pin if it drops below a defined threshold V_thun.
3.5 Undervoltage Reset Output (NRES)
This push-pull output is supplied from the V_CC voltage. If the V_CC voltage falls below the under-
voltage detection threshold of V_thun, NRES switches to low after tres_f (see Figure 4-7 on page
11) except the IC is switched into Sleep mode. Even if V_CC = 0V the NRES stays low, because it
is internally driven from the V_S voltage. If V_S voltage ramps down, NRES stays low until
V_S < 1.5V and then becomes highly resistive.
The implemented undervoltage delay keeps NRES low for t_Reset = 10 ms after V_CC reaches its
nominal value.
3.6 Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown, as well as an internal
pull-up resistor according to LIN specification 2.0 is implemented. The voltage range is from
–40V to +60V. This pin exhibits no reverse current from the LIN bus to V_S, even in the case of a
GND shift or V_Batt disconnection. The LIN receiver thresholds are compatible with the LIN proto-
col specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are
slope controlled. The output has a short-circuit limitation. This is a self-adapting current limita-
tion; that is, during current limitation, as the chip temperature increases, the current decreases.
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