AT45DB021B Datasheet, PDF (3/33 Pages) ATMEL Corporation – 2-megabit 2.7-volt Only DataFlash

AT45DB021B
Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0a = 8 Pages
2112 bytes (2K + 64)
SECTOR 0
BLOCK ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 2
8 Pages
SECTOR 0b = 248 Pages
65,472 bytes (62K + 1984)
SECTOR 0c = 256 Pages
67,584 bytes (64K + 2K)
SECTOR 1 = 512 Pages
135,168 bytes (128K + 4K)
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 126
BLOCK 127
Block = 2112 bytes
(2K + 64)
PAGE ARCHITECTURE
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 1021
PAGE 1022
PAGE 1023
Page = 264 bytes
(256 + 8)
Device Operation
Read Commands
The device operation is controlled by instructions from the host processor. The list of
instructions and their associated opcodes are contained in Tables 1 through 4 (pages 10
and 11). A valid instruction starts with the falling edge of CS followed by the appropriate
8-bit opcode and the desired buffer or main memory address location. While the CS pin
is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or
main memory address location through the SI (serial input) pin. All instructions,
addresses, and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA8 - BFA0 to
denote the nine address bits required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology PA9 -PA0 and BA8 -BA0 where
PA9 -PA0 denotes the 10 address bits required to designate a page address and BA8 -
BA0 denotes the nine address bits required to designate a byte address within the page.
By specifying the appropriate opcode, data can be read from the main memory or from
either one of the two data buffers. The DataFlash supports two categories of read
modes in relation to the SCK signal. The differences between the modes are in respect
to the inactive state of the SCK signal as well as which clock cycle data will begin to be
output. The two categories, which are comprised of four modes total, are defined as
Inactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPI
Mode 3. A separate opcode (refer to Table 1 on page 10 for a complete list) is used to
select which category will be used for reading. Please refer to the “Detailed Bit-level
Read Timing” diagrams in this datasheet for details on the clock cycle sequences for
each mode.
CONTINUOUS ARRAY READ: By supplying an initial starting address for the main
memory array, the Continuous Array Read command can be utilized to sequentially
read a continuous stream of data from the device by simply providing a clock signal; no
additional addressing information or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automatically increment on every clock
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1937F–DFLSH–10/02