AT28C16-T Datasheet, PDF (3/8 Pages) ATMEL Corporation – 16K 2K x 8 PCMCIA Nonvolatile Attribute Memory

AT28C16-T
Device Operation
READ:The AT28C16-T is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location detemined by the address pins is
asserted on the outputs. The outputs are put in a high im-
pedance state whenever CE or OE is high. This dual-line
control gives designers increased flexibility in preventing
bus contention.
BYTE WRITE: Writing data into the AT28C16-T is similar
to writing into a Static RAM. A low pulse on WE or CE input
with OE high and CE or WE low (respectively) initiates a
byte write. The address is latched on the falling edge of
WE or CE (whichever occurs last) and the data is latched
on the rising edge of WE or CE (whichever occurs first).
Once a byte write is started it will automatically time itself
to completion. For the AT28C16-T the write cycle time is 1
ms maximum. Once a programming operation has been
initiated and for the duration of tWC, a read operation will
effectively be a polling operation.
READY/BUSY: Pin 1 is an open drain READY/BUSY out-
put that indicates the current status of the self-timed inter-
nal write cycle. READY/BUSY is actively pulled low during
the write cycle and is released at the completion of the
write. The open drain output allows OR-tying of several
devices to a common interrupt input.
DATA POLLING: The AT28C16-T also provides DATA
polling to signal the completion of a write cycle. During a
write cycle, an attempted read of the the data being written
results in the complement of that data for I/O7 (the other
outputs are indeterminate). When the write cycle is fin-
ished, true data appears on all ouputs.
WRITE PROTECTION: Inadvertent writes to the device
are protected against in the following ways: (a) VCC
sense— if VCC is below 3.8V (typical) the write function is
inhibited; (b) VCC power on delay— once VCC h a s
reached 3.8V the device will automatically time out 5 ms
(typical) before allowing a byte write; (c) Write Inhibit—
holding any one of OE low, CE high or WE high inhibits
byte write cycles.
CHIP CLEAR: The contents of the entire memory of the
AT28C16-T may be set to the high state by the Chip Clear
operation. By setting CE low and OE to 12V, the chip is
cleared when a 10ms low pulse is applied to WE.
DEVICE IDENTIFICATION: A n e x t r a 3 2 - b y t e s o f
E²PROM memory are available to the user for device
identifcation. By raising A9 to 12V (± 0.5V) and using ad-
dress locations 7E0H to 7FFH the additional bytes may be
written to or read from in the same manner as the regular
memory array.
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