AT24C1024 Datasheet, PDF (3/19 Pages) ATMEL Corporation – 2-wire Serial EEPROM 1M (131,072 x 8)

AT24C1024
Pin Description
Memory
Organization
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/PAGE ADDRESSES (A1): The A1 pin is a device address input that can be hard-
wired or left not connected for hardware compatibility with AT24C128/256/512. When the A1
pin is hardwired, as many as two 1024K devices may be addressed on a single bus system
(device addressing is discussed in detail under the Device Addressing section). When the pin
is not hardwired, the default A1 is zero.
WRITE PROTECT (WP): The hardware Write Protect pin is useful for protecting the entire
contents of the memory from inadvertent write operations. The write-protect input, when tied to
GND, allows normal write operations. When WP is tied high to V_CC, all write operations to the
memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP
to V_CC prior to a write operation creates a software write-protect function.
AT24C1024, 1024K SERIAL EEPROM: The 1024K is internally organized as 512 pages of
256 bytes each. Random word addressing requires a 17-bit data word address.
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1471H–SEEPR–03/03