ATAR080 Datasheet, PDF (29/68 Pages) ATMEL Corporation – Low-current Microcontroller for Wireless Communication

ATAR080
Timer 1 Control Register 1
(T1C1)
Timer 1 Control Register 2
(T1C2)
T1C1
Bit 3 Bit 2
T1RM T1C2
Bit 3 = MSB, Bit 0 = LSB
Bit 1
T1C1
Bit 0
T1C0
Address: ’7’hex - Subaddress: ’8’hex
Reset value: 1111b
T1RM
T1C2
T1C1
T1C0
Timer 1 Restart Mode T1RM = 0, write access without Timer 1 restart
T1RM = 1, write access with Timer 1 restart
Note: if WDL = 0, Timer 1 restart is impossible
Timer 1 Control bit 2
Timer 1 Control bit 1
Timer 1 Control bit 0
The three bits T1C[2:0] select the divider for Timer 1. The resulting time interval
depends on this divider and the Timer 1 input clock source. The timer input can be sup-
plied by the system clock, the 32-kHz oscillator or via clock management. If the clock
management generates the SUBCL, the selected input clock from the RC-oscillator,
4-MHz oscillator or an external clock is divided by 16.
Table 13. Timer 1 Control Bits
T1C2 T1C1 T1C0 Divider
0
0
0
2
0
0
1
4
0
1
0
8
0
1
1
16
1
0
0
32
1
0
1
256
1
1
0 2048
1
1
1 16384
Time Interval with
SUBCL
SUBCL/2
SUBCL/4
SUBCL/8
SUBCL/16
SUBCL/32
SUBCL/256
SUBCL/2048
SUBCL/16384
Time Interval with Time Interval with
SUBCL = 32 kHz SYSCL = 2/1 MHz
61 µs
1 µs/2 µs
122 µs
2 µs/4 µs
244 µs
4 µs/8 µs
488 µs
8 µs/16 µs
0.977 ms
16 µs/32 µs
7.812 ms
128 µs/256 µs
62.5 ms
1024 µs/2048 µs
500 ms
8192 µs/16384 µs
Bit 3
T1C2 –
Bit 2
T1BP
Bit 3 = MSB, Bit 0 = LSB
Bit 1
T1CS
Bit 0
T1IM
Address: ’7’hex - Subaddress: ’9’hex
Reset value: x111b
T1BP
T1CS
T1IM
Timer 1 SUBCL ByPassed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
Timer 1 input Clock Select
T1CS = 1, CL1 = SUBCL (see Figure 28 on page 28)
T1CS = 0, CL1 = SYSCL (see Figure 28 on page 28)
Timer 1 Interrupt Mask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
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4675D–4BMCU–12/04