AT90USB82 Datasheet, PDF (29/306 Pages) ATMEL Corporation – 8-bit Microcontroller with 8/16K Bytes of ISP Flash

AT90USB82/162
6.2.5
Clock Status Register – CLKSTA
Bit
7
-
Read/Write
R
Initial Value
0
6
5
4
3
2
-
-
-
-
-
R
R
R
R
R
0
0
0
See Bit Description
• Bit 7-2 - Reserved bits
These bits are reserved and will always read as zero.
1
RCON
R
0
EXTON
R
CLKSTA
• Bit 1 – RCON: RC Oscillator On
This bit is set by hardware to one if the RC Oscillator is running.
This bit is set by hardware to zero if the RC Oscillator is stoped.
• Bit 0 – EXTON: External Oscillator / Low Power Oscillator On
This bit is set by hardware to one if the External Oscillator / Low Power Oscillator is running.
This bit is set by hardware to zero if the External Oscillator / Low Power Oscillator is stoped.
6.3 Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6-1. Device Clocking Options Select⁽¹⁾
Device Clocking Option
Low Power Crystal Oscillator
Reserved
Reserved
Reserved
Calibrated Internal RC Oscillator
External Clock
Reserved
CKSEL3..0
1111 - 1000
0111 - 0110
0101 - 0100
0011
0010
0000
0001
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
6.3.1
Default Clock Source
The device is shipped with internal RC oscillator at 8.0 MHz and with the fuse CKDIV8 pro-
grammed, resulting in 1.0 MHz system clock. The startup time is set to maximum and time-out
period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that
all users can make their desired clock source setting using any available programming interface.
6.3.2
Clock Startup Sequence
Any clock source needs a sufficient V_CC to start oscillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient V_CC, the device issues an internal reset with a time-out delay (t_TOUT) after
the device reset is released by all other reset sources. “On-chip Debug System” on page 45
describes the start conditions for the internal reset. The delay (t_TOUT) is timed from the Watchdog
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
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7707D–AVR–07/08