AT32UC3A0512_08 Datasheet, PDF (29/86 Pages) ATMEL Corporation – AVR32 32-Bit Microcontroller

AT32UC3A
10.4.3 SPIs
Each SPI can be connected to an internally divided clock:
Table 10-6.
SPI
0
1
SPI clock connections
Source
Name
Internal
CLK_DIV
Connection
PBA clock or
PBA clock / 32
10.5 Nexus OCD AUX port connections
If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-
spectively of the PIO configuration. Two different OCD trace pin mappings are possible,
depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Tech-
nical Reference Manual.
Table 10-7.
Pin
EVTI_N
MDO[5]
MDO[4]
MDO[3]
MDO[2]
MDO[1]
MDO[0]
EVTO_N
MCKO
MSEO[1]
MSEO[0]
Nexus OCD AUX port connections
AXS=0
AXS=1
PB19
PA08
PB16
PA27
PB14
PA26
PB13
PA25
PB12
PA24
PB11
PA23
PB10
PA22
PB20
PB20
PB21
PA21
PB04
PA07
PB17
PA28
10.6 PDC handshake signals
The PDC and the peripheral modules communicate through a set of handshake signals. The fol-
lowing table defines the valid settings for the Peripheral Identifier (PID) in the PDC Peripheral
Select Register (PSR).
Table 10-8.
PID Value
0
1
2
3
PDC Handshake Signals
Peripheral module & direction
ADC
SSC - RX
USART0 - RX
USART1 - RX
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