AT91M42800A_0203 Datasheet, PDF (28/198 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

Boot on NCS0
Figure 14 shows how to connect a 16-bit device without byte access (e.g., Flash) on
NCS2.
Figure 14. Connection for a 16-bit Data Bus without Byte Write Capability
D0 - D7
D8 - D15
A1 - A19
EBI
NLB
NUB
NWE
NOE
NCS2
D0 - D7
D8 - D15
A0 - A18
Write Enable
Output Enable
Memory Enable
Depending on the device and the BMS pin level during the reset, the user can select
either an 8-bit or 16-bit external memory device connected on NCS0 as the Boot mem-
ory. In this case, EBI_CSR0 (Chip Select Register 0) is reset at the following
configuration for chip select 0:
• 0 wait states (WSE = 0, NWS = 7)
• 8-bit or 16-bit data bus width, depending on BMS
Byte access type and number of data float time are set to Byte Write Access and 0,
respectively.
Before the remap command, the user can modify the chip select 0 configuration, pro-
gramming the EBI_CSR0 with the exact Boot memory characteristics. The base
address becomes effective after the remap command.
Warning: In the internal oscillator bypass mode described in “Operating Modes” on
page 11, the user must take the external oscillator frequency into account according to
the minimum access time on the boot memory device.
As illustration, the following table gives examples of oscillator frequency limits according
to the time access without using NWAIT pin at the boot.
Chip Select Assertion to Output Data Valid
Maximum Delay in Read Cycle (t_CE in ns)
110
90
70
55
25
Note: Values take only t_CE into account.
External Oscillator
Frequency Limit (MHz)
7
9
11
14
24
28 AT91M42800A
1779B–ATARM–03/02