AT91M40800_1 Datasheet, PDF (28/153 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

Figure 15. Early Read Protocol
MCKI
ADDR
NCS
NRD
or
NWE
Figure 16. Early Read Wait State
Write Cycle
MCKI
Early Read Wait
Read Cycle
ADDR
NCS
NRD
NWE
Write Data Hold Time
During write cycles in both protocols, output data becomes valid after the falling edge of
the NWE signal and remains valid after the rising edge of NWE, as illustrated in Figure
17. The external NWE waveform (on the NWE pin) is used to control the output data tim-
ing to guarantee this operation.
It is therefore necessary to avoid excessive loading of the NWE pins, which could delay
the write signal too long and cause a contention with a subsequent read cycle in stan-
dard protocol.
28 AT91X40 Series
1354D–ATARM–05/02