AT91C140 Datasheet, PDF (28/171 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

SDRAM Controller (SDRAMC)
Description
Block Diagram
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by provid-
ing the interface to an external 16-bit or 32-bit SDRAM device. The page size supports
ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte
(8-bit), half-word (16-bit) and word (32-bit) accesses. The maximum addressable
SDRAM size is 256M bytes.
The SDRAM Controller supports a read or write burst length of one location. It keeps
track of the active row in each bank, thus maximizing SDRAM performance, e.g., the
application may be placed in one bank and data in the other banks. So as to optimize
performance, it is advisable to avoid accessing different rows in the same bank.
Figure 10. SDRAM Controller Block Diagram
SDRAMC
Memory
Controller
SDRAMC
Chip Select
System
Controller
ACLK
User Interface
SDCK
SDCS
BA[1:0]
RAS
CAS
WE
DQM[3:0]
A[12:11, 9:0]
SDA10
D[31:0]
APB
28 _AT91C140
6069A–ATARM–05/04