ATSAM3U_10 Datasheet, PDF (27/62 Pages) ATMEL Corporation – AT91ARM Cortex M3-based Microcontrollers

SAM3U Series
7.4 Matrix Slaves
The Bus Matrix of the SAM3U manages 10 slaves. Each slave has its own arbiter, allowing a dif-
ferent arbitration per slave.
Table 7-2.
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
Slave 5
Slave 6
Slave 7
Slave 8
Slave 9
List of Bus Matrix Slaves
Internal SRAM0
Internal SRAM1
Internal ROM
Internal Flash 0
Internal Flash 1
USB Device High Speed Dual Port RAM (DPR)
NAND Flash Controller RAM
External Bus Interface
Low Speed Peripheral Bridge
High Speed Peripheral Bridge
7.5 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the USB Device High speed DMA to the Internal Peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “–” in Table 7-3 below.
Table 7-3. SAM3U Master to Slave Access
0
1
Slaves
0
1
2
3
4
5
6
7
8
9
Cortex-M3
Masters I/D Bus
Internal SRAM0
–
Internal SRAM1
–
Internal ROM
X
Internal Flash 0
X
Internal Flash 1
X
USB Device High Speed Dual Port RAM (DPR)
–
NAND Flash Controller RAM
–
External Bus Interface
–
Low Speed Peripheral Bridge
–
High Speed Peripheral Bridge
–
Cortex-M3 S
Bus
X
X
–
–
–
X
X
X
X
X
2
PDC
X
X
X
–
–
–
X
X
X
X
3
USB Device
High Speed
DMA
X
X
X
–
–
–
X
X
–
–
4
DMA
Controller
X
X
X
–
–
–
X
X
–
–
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6430CS–ATARM–09-Apr-10