AT91M55800A Datasheet, PDF (27/227 Pages) ATMEL Corporation – ARM Thumb Microcontrollers

Read Protocols
Standard Read Protocol
AT91M55800A
The EBI provides two alternative protocols for external memory read access: standard
and early read. The difference between the two protocols lies in the timing of the NRD
(read cycle) waveform.
The protocol is selected by the DRP field in EBI_MCR (Memory Control Register) and is
valid for all memory devices. Standard read protocol is the default protocol after reset.
Note:
In the following waveforms and descriptions, NRD represents NRD and NOE since the
two signals have the same waveform. Likewise, NWE represents NWE, NWR0 and
NWR1 unless NWR0 and NWR1 are otherwise represented. ADDR represents A0 - A23
and/or A1 - A23.
Standard read protocol implements a read cycle in which NRD and NWE are similar.
Both are active during the second half of the clock cycle. The first half of the clock cycle
allows time to ensure completion of the previous access as well as the output of address
and NCS before the read cycle begins.
During a standard read protocol, external memory access, NCS is set low and ADDR is
valid at the beginning of the access while NRD goes low only in the second half of the
master clock cycle to avoid bus conflict (see Figure 11). NWE is the same in both proto-
cols. NWE always goes low in the second half of the master clock cycle (see Figure 12).
Figure 11. Standard Read Protocol
MCK
ADDR
NCS
NRD
or
NWE
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