ATMEGA128_09 Datasheet, PDF (265/386 Pages) ATMEL Corporation – 8-bit Microcontroller with 128K Bytes In-System Programmable Flash

ATmega128
The recommended values from Table 104 are used unless other values are given in the algo-
rithm in Table 105. Only the DAC and Port Pin values of the Scan Chain are shown. The column
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Table 105. Algorithm for Using the ADC
Step
1
2
3
4
5
6
7
8
9
10
11
Actions
SAMPLE_
PRELOAD
EXTEST
Verify the
COMP bit
scanned
out to be 0
Verify the
COMP bit
scanned
out to be 1
ADCEN
1
1
1
1
1
1
1
1
1
1
1
DAC
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
HOLD
1
0
1
1
1
1
0
1
1
1
1
PRECH
1
1
1
1
0
1
1
1
1
0
1
PA3.
Data
0
0
0
0
0
0
0
0
0
0
0
PA3.
Control
0
0
0
0
0
0
0
0
0
0
0
PA3.
Pullup_
Enable
0
0
0
0
0
0
0
0
0
0
0
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t_hold,max
2467S–AVR–07/09
265