ATA6020N_14 Datasheet, PDF (26/68 Pages) ATMEL Corporation – Low-current Microcontroller for Watchdog Function

4.2.4
Universal Timer/Counter/ Communication Module (UTCM)
The universal timer/counter/communication module (UTCM) consists of timer 1, timer 2 and a synchronous serial interface
(SSI).
● Timer 1 is an interval timer that can be used to generate periodical interrupts and as prescaler for timer 2, the serial
interface and the watchdog function.
● Timer 2 is an 8/12-bit timer with an external clock input (T2I) and an output (T2O).
● The SSI operates as a two-wire serial interface or as a shift register for modulation. The modulator units work together
with the timers and shift the data bits out of the shift register.
There is a multitude of modes in which the timers and the serial interface can work together.
Figure 4-6. UTCM Block Diagram
SYSCL
SUBCL
from clock module
Timer 1
MUX
Watchdog
Interval/Prescaler
NRST
INT2
T1OUT
Timer 2
MUX
POUT
4-bit Counter 2/1
Compare 2/1
Control
Modulator
2
T2O
I/O bus
T2I
8-bit Counter 2/2
MUX DCG
INT4
Compare 2/2
TOG2
MUX
SSI
Receive buffer
8-bit Shift register
Transmit buffer
SCL
Control
SC
SD
INT3
4.2.5
Timer 1
Timer 1 is an interval timer which can be used to generate periodic interrupts and as a prescaler for timer 2, timer 3, the
serial interface and the watchdog function.
Timer 1 consists of a programmable 14-stage divider that is driven by either SUBCL or SYSCL. The timer output signal can
be used as a prescaler clock or as SUBCL and as source for the timer 1 interrupt. Because of other system requirements
timer 1 output T1OUT is synchronized with SYSCL. Therefore, in the power-down mode SLEEP (CPU core -> sleep and
OSC-Stop -> yes) the output T1OUT is stopped (T1OUT = 0). Nevertheless, timer 1 can be active in SLEEP and generate
timer 1 interrupts. The interrupt is maskable via the T1IM bit and the SUBCL can be bypassed via the T1BP bit of the T1C2
register. The time interval for the timer output can be programmed via the timer 1 control register T1C1.
This timer starts running automatically after any power-on reset! If the watchdog function is not activated, the timer can be
restarted by writing into the T1C1 register with T1RM = 1.
Timer 1 can also be used as a watchdog timer to prevent a system from stalling. The watchdog timer is a 3-bit counter that is
supplied by a separate output of timer 1. It generates a system reset when the 3-bit counter overflows. To avoid this, the
3-bit counter must be reset before it overflows. The application software has to accomplish this by reading the CWD register.
After power-on reset the watchdog must be activated by software in the $RESET initialization routine. There are two
watchdog modes, in one mode the watchdog can be switched on and off by software, in the other mode the watchdog is
active and locked. This mode can only be stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval for the watchdog reset can be programmed via the watchdog
control register (WDC).
26 ATA6020N [ DATASHEET]
4708F–4BMCU–10/14