AT86RF230 Datasheet, PDF (25/50 Pages) ATMEL Corporation – ZigBee/IEEE 802.15.4-Transceiver

AT86RF230
7. PHY to Micro-Controller Interface
In the following paragraphs, the PHY to micro-controller interface is defined. The SPI protocol and timing access
are shown, as well as buffer access modes with examples.
Controllers with an SPI interface such as an AVR will work with the AT86RF230 interface. The SPI interface is
used for both register programming as well as for frame transfer. The additional control signals are connected to
the GPIO interface of the controller. Figure 7-1 shows the signals which need to be connected between the
controller and the transceiver. The CLKM signal can be used as a controller main clock (synchronous mode) or as
software timer reference (asynchronous mode).
Micro-Controller
SEL
MOSI
MISO
SCLK
SEL
MOSI
MISO
SCLK
AT86RF230
SEL
MOSI
MISO
SCLK
GPIO1/CLK
GPIO2/IRQ
GPIO3
GPIO4
CLKM
IRQ
SLP_TR
RST
CLKM
IRQ
SLP_TR
RST
Figure 7-1. PHY-HOST Interface
7.1. SPI Protocol
SPI is used to program control registers as well as to transfer data frames between the controller and the
AT86RF230. The additional signals CLKM, IRQ, SLP_TR and RST are connected to the GPIO interface of the
controller.
The internal 128-byte frame buffer can keep one TX or one RX frame of maximum length at a time. This offers a
very flexible data rate over the SPI interface.
SEL
SCLK
MISO
MOSI
SLP_TR
t1
t2
t5
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
t3
t4
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
t6
t7
Figure 7-2. SPI Timing
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