ATMEGA329P_06 Datasheet, PDF (243/360 Pages) ATMEL Corporation – 8-bit Microcontroller with 32K Bytes In-System Programmable Flash

ATmega329P/3290P
Table 21-4.
LCDPS2
1
1
1
LCD Prescaler Select (Continued)
LCDPS1
0
1
1
LCDPS0
1
0
1
Output from
Prescaler
clk_LCD/N
clk_LCD/1024
clk_LCD/2048
clk_LCD/4096
• Bit 3 – Res: Reserved Bit
This bit is reserved and will always read as zero.
Applied Prescaled LCD Clock Frequency
when LCDCD2:0 = 0, Duty = 1/4, and
Frame Rate = 64 Hz
520 kHz
1 MHz
2 MHz
• Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0
The LCDCD2:0 bits determine division ratio in the clock divider. The various selections are
shown in Table 21-5. This Clock Divider gives extra flexibility in frame rate selection.
Table 21-5. LCD Clock Divide
LCDCD2
0
0
0
0
1
1
1
1
LCDCD1
0
0
1
1
0
0
1
1
LCDCD0
0
1
0
1
0
1
0
1
Output from
Prescaler
divided by (D) :
1
2
3
4
5
6
7
8
clk_LCD = 32.768 kHz, N = 16, and Duty =
1/4, gives a frame rate of:
256 Hz
128 Hz
85.3 Hz
64 Hz
51.2 Hz
42.7 Hz
36.6 Hz
32 Hz
The frame frequency can be calculated by the following equation:
f_frame
=
------^f-^c---^l--^k--^L--^C---^D------
(K ⋅ N ⋅ D)
Where:
N = prescaler divider (16, 64, 128, 256, 512, 1024, 2048, or 4096).
K = 8 for duty = 1/4, 1/2, and static.
K = 6 for duty = 1/3.
D = Division factor (see Table 21-5 on page 243)
This is a very flexible scheme, and users are encouraged to calculate their own table to investi-
gate the possible frame rates from the formula above. Note when using 1/3 duty the frame rate
8021A–AVR–12/06
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