JTAGICE3 Datasheet, PDF(24/40 Page) ATMEL Corporation – Programming and on-chip debugging of all Atmel AVR 32-bit Microcontrollers on both JTAG and aWire interfaces

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JTAGICE3 Datasheet, PDF (24/40 Pages) ATMEL Corporation – Programming and on-chip debugging of all Atmel AVR 32-bit Microcontrollers on both JTAG and aWire interfaces

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Figure 4-9.âRecommended ARM SWD/JTAG Header Pinout

The JTAGICE3 is capable of streaming UART-format ITM trace to the host computer. Trace is captured

on the TRACE/SWO pin of the 10-pin header (JTAG TDO pin). Data is buffered internally on the

JTAGICE3 and is sent over the HID interface to the host computer. The maximum reliable data rate is

approx. 1MB/s.

4.3. Atmel OCD Implementations

4.3.1.

Atmel AVR UC3 OCD (JTAG and aWire)

The Atmel AVR UC3 OCD system is designed in accordance with the Nexus 2.0 standard (IEEE-ISTO

5001â¢-2003), which is a highly flexible and powerful open on-chip debug standard for 32-bit

microcontrollers. It supports the following features:

â¢ Nexus compliant debug solution

â¢ OCD supports any CPU speed

â¢ Six program counter hardware breakpoints

â¢ Two data breakpoints

â¢ Breakpoints can be configured as watchpoints

â¢ Hardware breakpoints can be combined to give break on ranges

â¢ Real-time program counter branch tracing, data trace, process trace (not supported by Atmel

JTAGICE3)

For more information regarding the UC3 OCD system, consult the AVR32UC Technical Reference

Manuals, located on www.atmel.com/uc3.

4.3.2.

Atmel AVR XMEGA OCD (JTAG and PDI physical)

The Atmel AVR XMEGA OCD is otherwise known as PDI (Program and Debug Interface). Two physical

interfaces (JTAG and PDI physical) provide access to the same OCD implementation within the device. It

supports the following features:

â¢ Complete program flow control

â¢ One dedicated program address comparator or symbolic breakpoint (reserved)

â¢ Four hardware comparators

â¢ Unlimited number of user program breakpoints (using BREAK)

â¢ No limitation on system clock frequency

4.3.3.

Atmel megaAVR OCD (JTAG)

The Atmel megaAVR OCD is based on the JTAG physical interface. It supports the following features:

â¢ Complete program flow control

â¢ Four program memory (hardware) breakpoints (one is reserved)

â¢ Hardware breakpoints can be combined to form data breakpoints

Atmel JTAGICE3 [USER GUIDE] 24

Atmel-42634B-JTAGICE3_User Guide-10/2016

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