AVR1300 Datasheet, PDF (24/26 Pages) ATMEL Corporation – Up to 12 bit resolution Signed and unsigned mode Result comparator

4.3 Free-running Mode
Task: Free-running differential conversion on channel 0, using ADC0 and ADC3 as
positive and negative inputs.
• Set the MUX Positive Input and MUX Negative Input bitfields (MUXPOS and
MUXNEG) in Channel 0 (CH0MUXCTRL) to 0x00 and 0x03 respectively.
• Set the Free Run bit (FREERUN) in Control Register B (CTRLB) to enable free
running mode.
• Set the Enable bit (ENABLE) in Control Register A (CTRLA) to enable the ADC
module without calibrating. Wait for the ADC start-up time (typ. max 24 ADC
clocks).
• Optionally wait for the Interrupt Flag bit for channel 0 (CH0IF) in the Interrupt
Flags register (INTFLAGS) to be set, indicating that a new conversion is finished.
Clear the flag by writing a one to it, as it is going to be used later.
• Read the Result register pair for channel 0 (CH0RESL/CH0RESH) to retrieve the
latest 12-bit conversion results as a 2-byte value.
Note that it is not strictly required to wait for the interrupt flag when using free-running
mode. However, to make sure you have a fresh conversion, you should wait for the
flag, clear it and then read the result. Also note that it is recommended to use the
Free-running Mode together with DMA data transfer to offload work from the CPU.
5 Advanced Features
This section introduces more advanced features and possibilities with the ADC. In-
depth treatment is outside the scope of this application note and the user is advised
to study the device datasheet and relevant application notes.
5.1 DMA Controller
Instead of using interrupt handlers to read and process the result registers, it is
possible to use the Atmel^® AVR^® XMEGA^® DMA Controller to move data from one or
more result registers to memory buffers or other peripheral modules. This moving of
data is done without CPU intervention, and leaves the CPU ready for other tasks,
even without having to execute interrupt handlers.
For more information, please refer to the device datasheet or the application note
“AVR1304: Getting Started with the XMEGA DMA Controller”.
5.2 Event System
To improve conversion timing and further offload work from the CPU, the ADC is
connected to the XMEGA Event System. This makes it possible to use incoming
events to trigger single conversions or conversion sweeps across several channels.
The ADC conversion complete conditions also serve as event sources available for
other peripheral modules connected to the event system.
For more information, please refer to the device datasheet or the application note
“AVR1001: Getting Started with the XMEGA Event System”.
24 _AVR1300
8032H-AVR-12/10