ATTINY28L Datasheet, PDF (24/75 Pages) ATMEL Corporation – 8-bit AVR Microcontroller with 2K Bytes of Flash

Timer/Counter0 Control
Register – TCCR0
The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external
pin. In addition, it can be stopped as described in the specification for the
Timer/Counter0 Control Register (TCCR0). The overflow status flag is found in the Inter-
rupt Flag Register (IFR). Control signals are found in the Timer/Counter0 Control
Register (TCCR0). The interrupt enable/disable setting for Timer/Counter0 is found in
the Interrupt Control Register (ICR).
When Timer/Counter0 is externally clocked, the external signal is synchronized with the
oscillator frequency of the CPU. To ensure proper sampling of the external clock, the
minimum time between two external clock transitions must be at least one internal CPU
clock period. The external clock signal is sampled on the rising edge of the internal CPU
clock.
The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage
with the lower prescaling opportunities. Similarly, the high prescaling opportunities make
the Timer/Counter0 useful for lower speed functions or exact timing functions with infre-
quent actions.
Bit
7
6
$04
FOV0
–
Read/Write
R/W
R
Initial Value
0
0
5
4
3
2
1
0
–
OOM01 OOM00 CS02 CS01 CS00 TCCR0
R
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
• Bit 7 – FOV0: Force Overflow
Writing a logical “1” to this bit forces a change on the overflow output pin PA2 according
to the values already set in OOM01 and OOM00. If the OOM01 and OOM00 bits are
written in the same cycle as FOV0, the new settings will not take effect until the next
overflow or forced overflow occurs. The Force Overflow bit can be used to change the
output pin without waiting for an overflow in the timer. The automatic action programmed
in OOM01 and OOM00 happens as if an overflow had occurred, but no interrupt is gen-
erated. The FOV0 bit will always read as zero, and writing a zero to this bit has no effect.
• Bits 6, 5 – Res: Reserved Bits
These bits are reserved bits in the ATtiny28 and always read as zero.
• Bits 4, 3 – OOM01, OOM00: Overflow Output Mode, Bits 1 and 0
The OOM01 and OOM00 control bits determine any output pin action following an over-
flow or a forced overflow in Timer/Counter0. Any output pin actions affect pin PA2. The
control configuration is shown in Table 9.
Table 9. Overflow Output Mode Select
OOM01
OOM00 Description
0
0
Timer/Counter0 disconnected from output pin PA2
0
1
Toggle the PA2 output line.
1
0
Clear the PA2 output line to zero.
1
1
Set the PA2 output line to one.
• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0
The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0.
24 ATtiny28L/V
1062E–10/01