ATAM862-3_07 Datasheet, PDF (24/110 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

A power-on reset pulse is generated by a V_DD rise across the default BOT voltage level (1.7V). A
brown-out reset pulse is generated when V_DD falls below the brown-out voltage threshold. Two
values for the brown-out voltage threshold are programmable via the BOT bit in the SC register.
When the controller runs in the upper supply voltage range with a high system clock frequency,
the high threshold must be used. When it runs with a lower system clock frequency, the low
threshold and a wider supply voltage range may be chosen. For further details, see the electrical
specification and the SC register description for BOT programming.
Figure 17-2. Brown-out Detection
V_DD
2.0V
1.7V
t_d
CPU
Reset BOT = '1'
t_d
CPU
Reset BOT = '0'
t
t_d
td = 1.5 ms (typically)
BOT = 1, low brown-out voltage threshold 1.7V (is reset value).
BOT = 0, high brown-out voltage threshold 2.0V.
17.1.1
Watchdog Reset
The watchdog’s function can be enabled at the WDC register and triggers a reset with every
watchdog counter overflow. To suppress the watchdog reset, the watchdog counter must be
regularly reset by reading the watchdog register address (CWD). The CPU reacts in exactly the
same manner as a reset stimulus from any of the above sources.
17.1.2
External Clock Supervisor
The external input clock supervisor function can be enabled if the external input clock is selected
within the CM and SC registers of the clock module. The CPU reacts in exactly the same man-
ner as a reset stimulus from any of the above sources.
18. Voltage Monitor
The voltage monitor consists of a comparator with internal voltage reference. It is used to super-
vise the supply voltage or an external voltage at the VMI pin. The comparator for the supply
voltage has three internal programmable thresholds one lower threshold (2.2V), one middle
threshold (2.6V) and one higher threshold (3.0V). For external voltages at the VMI pin, the com-
parator threshold is set to V_BG = 1.3V. The VMS bit indicates if the supervised voltage is below
(VMS = 0) or above (VMS = 1) this threshold. An interrupt can be generated when the VMS bit is
set or reset to detect a rising or falling slope. A voltage monitor interrupt (INT7) is enabled when
the interrupt mask bit (VIM) is reset in the VMC register.
24 ATAM862-3
4554F–4BMCU–07/07