AT83SND2CMP3A1_14 Datasheet, PDF (24/98 Pages) ATMEL Corporation – CRC Error and MPEG Frame Synchronization Indicators

Figure 24. Serial Audio Interface
Audio
DAC
Audio
PA
AUDCDIN
AUDCDOUT
AUDCCLK
AUDCCS
Protocol is as following to access DAC registers:
Figure 25. Dac SPI Interface
AUDCCS
AUDCCLK
AUDCDIN
rw a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0
AUDCDOUT
d7 d6 d5 d4 d3 d2 d1 d0
DAC Interface SPI Protocol
On AUDCDIN, the first bit is a read/write bit. 0 indicates a write operation while 1 is for a
read operation. The 7 following bits are used for the register address and the 8 last ones
are the write data. For both address and data, the most significant bit is the first one.
In case of a read operation, AUDCDOUT provides the contents of the read register,
MSB first.
The transfer is enabled by the AUDCCS signal active low. The interface is resetted at
every rising edge of AUDCCS in order to come back to an idle state, even if the transfer
does not succeed. The DAC Interface SPI is synchronized with the serial clock AUDC-
24 AT83SND2CMP3
7524D–MP3–07/07