AT73C213B_14 Datasheet, PDF (24/37 Pages) ATMEL Corporation – 93 dB SNR Playback Stereo Channels

8.14 DAC Clock and Sampling Frequency Control Register
Register Name: DAC_CSFC
Reset State: 0x00
Access: Read/Write
7
6
5
4
3
2
1
0
0
0
0
OVRSEL
0
0
0
0
• OVRSEL: Master clock selector
L to 256 x Fs, H to 384 x Fs
Master clock and sampling frequency selection
Table 8-4 describes the modes available for master clock and sampling frequency selection.
Table 8-4.
OVRSEL
0
1
Master Clock Modes
Master Clock
256 x Fs
384 x Fs
24 AT73C213B
6407A–PMAAC–22-Apr-08