AT69170E Datasheet, PDF (24/28 Pages) ATMEL Corporation – Space FPGA Configuration Memory

9.4.2
FPGA Configuration characteristics & waveform - Memory Dump
Figure 9-2. FPGA Configuration with AT69170E - Memory Dump
CE
RESET/OE
CLK
DATA
RESET/OE
T_SCE
T_SCE
T_LC
T_HC
T_HOE
T_OE
T_CE
T_CAC
T_OH
Figure 9-3. FPGA Configuration - AT69170E cascade mode
T_DF
T_OH
T_HCE
CE
CLK
DATA
CEO
T_CDF
LAST BIT
T_OCK
T_OCE
Table 9-2. FPGA Configuration timings
Symbol
T_OE
T_CE
T_CAC
T_OH
T_DF
Tcdf
Description
Data Output Delay from OE
Data Output Delay from CE
Data Output Delay from CLK
Data Hold from CE, OE, or CLK
Data Float Output Delay from CE or OE
Data Float Output Delay from CLK
T_OCE
26 AT69170E
T_OOE
FIRST BIT
AT69170E
Min
Max
35
40
40
0
30
30
Units
ns
ns
ns
ns
ns
ns
7752A–AERO–07/07