AT90SCR100_09 Datasheet, PDF (235/433 Pages) ATMEL Corporation – 8-bit Microcontroller for Smart Card Readers

AT90SCR100
18.4.3
External Clock
External clocking is used by the synchronous slave modes of operation. The description in this
section refers to Figure 18-2 for details.
External clock input from the XCK pin is sampled by a synchronization register to minimize the
chance of meta-stability. The output from the synchronization register must then pass through
an edge detector before it can be used by the Transmitter and Receiver. This process intro-
duces a two CPU clock period delay and therefore the maximum external XCK clock frequency
is limited by the following equation:
f_XCK < -^f-^O---₄-^S---^C--
18.4.4
Synchronous Clock Operation
When synchronous mode is used (UMSEL0 = 1), the XCK pin will be used as either clock input
(Slave) or clock output (Master). The dependency between the clock edges and data sampling
or data change is the same. The basic principle is that data input (on RxD0) is sampled at the
opposite XCK clock edge of the edge the data output (TxD0) is changed.
Figure 18-3. Synchronous Mode XCK Timing.
UCPOL = 1 XCK
RxD / TxD
UCPOL = 0 XCK
Sample
RxD / TxD
Sample
The UCPOL0 bit UCRSC selects which XCK clock edge is used for data sampling and which is
used for data change. As Figure 18-3 shows, when UCPOL0 is zero the data will be changed at
rising XCK edge and sampled at falling XCK edge. If UCPOL0 is set, the data will be changed at
falling XCK edge and sampled at rising XCK edge.
18.5
Frame Formats
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
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