U4091BM-N Datasheet, PDF (23/38 Pages) ATMEL Corporation – PROGRAMMABLE TELEPHONE AUDIO PROCESSOR

Analog-to-Digital
Converter ADC
U4091BM-N
This circuit is a 7-bit successive approximation analog-to-digital converter in switched
capacitor technique. An internal band gap circuit generates a 1.25-V reference voltage
which is the equivalent of 1 MSB. 1LSB = 19.5 mV. The possible input voltage at ADIN
is 0 to 2.48 V.
The ADC needs an SOC (Start Of Conversion) signal. In the High phase of the SOC sig-
nal, the ADC is reset. Then, 50 µs after the beginning of the Low phase of the SOC
signal, the ADC generates an EOC (End Of Conversion) signal which indicates that the
conversion is finished. The rising edge of EOC generates an interrupt at the INT output.
The result can be read out by the serial bus.
Voltages higher than 2.45 V have to be divided. The signal connected to the ADC is
determined by 4 bits: ADC0, ADC1, ADC2 and ADC3. TLDR/TLDT measuring is possi-
ble relative to a preceding reference measurement. The current range of IL can be
doubled by ADCR. If ADCR is High, S has the value 0.5, otherwise S = 1.
The source impedance at ADIN must be lower than 250 kΩ.
Accuracy: 1 LSB + 3%
Figure 17. Timing of ADC
SOC
50 µs
EOC
Figure 18. ADC Input Selection
IL x 20mV/(1mA x S)
ADIN
0.4 x VB
0.4 x VMPS
0.4 x VMP
8 x (TLDR-REF)
8 x (TLDT-REF)
0.4 x SAO1
0.4 x OFF1
0.4 x OFF2
0.4 x OFF3
SOC
ADC
EOC
MSB
BIT5
BIT4
BIT3
BIT2
BIT1
LSB
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