AT91SAM9260_06 Datasheet, PDF (23/45 Pages) ATMEL Corporation – Thumb Microcontrollers

AT91SAM9260 Preliminary
The AT91SAM9260 matrix manages a boot memory that depends on the level on the BMS pin
at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is
reserved for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
8.1.1.1
BMS = 1, Boot on Embedded ROM
The system boots using the Boot Program.
• Boot on slow clock (On-chip RC or 32,768 Hz)
• Auto baudrate detection
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader on a non-volatile memory
– SPI DataFlash^® connected on NPCS0 and NPCS1 of the SPI0
– 8-bit and/or 16-bit NANDFlash
• SAM-BA^™ Boot in case no valid program is detected in external NVM, supporting
– Serial communication on a DBGU
– USB Device Port
8.1.1.2
BMS = 0, Boot on External Memory
• Boot on slow clock (On-chip RC or 32,768 Hz)
• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-
bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile
memory.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must
take the following steps:
1. Program the PMC (main oscillator enable or bypass mode).
2. Program and start the PLL.
3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them
to the new clock.
4. Switch the main clock to the new value.
8.2 External Memories
The external memories are accessed through the External Bus Interface. Each Chip Select
line has a 256-Mbyte memory area assigned.
Refer to the memory map in Figure 8-1 on page 21.
8.2.1
External Bus Interface
• Integrates three External Memory Controllers
– Static Memory Controller
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6221DS–ATARM–22-Sep-06