TSC21020F Datasheet, PDF (22/50 Pages) ATMEL Corporation – Rad. Hard 32/40-bit IEEE Floating Point DSP

Table 5. Universal Registers
Name
Function
Register file
R15-R0
Register file locations
Program Sequencer
PC⁽¹⁾
Program counter; address of instruction currently executing
PCSTK
Top of PC stack
PCSTKP
FADDR⁽¹⁾
DADDR⁽¹⁾
PC stack pointer
Fetch address
Decode address
LADDR
Loop termination address, code; top of loop address stack
CURLCNTR Current loop counter; top of loop count stack
LCNTR
Loop count for next nested counter-controlled loop
Data Address Generators
I7-I0
DAG1 index registers
M7-M0
DAG1 modify registers
L7-L0
DAG1 length registers
B7-B0
DAG1 base registers
I15-I8
DAG2 index registers
M15-M8
DAG2 modify registers
L15-L8
DAG2 length registers
B15-B8
DAG2 base registers
Bus Exchange
PX1
PMD-DMD bus exchange 1 (16 bits)
PX2
PMD-DMD bus exchange 2 (32 bits)
PX
48-bit PX1 and PX2 combination
Timer
TPERIOD
Timer period
TCOUNT
Timer counter
Memory Interface
DMWAIT
Wait state and page size control for data memory
DMBANK1
Data memory bank 1 upper boundary
DMBANK2
Data memory bank 2 upper boundary
22 TSC21020F
4153H–AERO–04/07