ATAR862-8_07 Datasheet, PDF (22/112 Pages) ATMEL Corporation – Microcontroller with UHF ASK/FSK Transmitter

Table 16-2. Hardware Interrupts
Interrupt
INT1
INT2
INT3
INT4
INT5
INT6
INT7
Register
P5CR
T1M
SISC
T2CM
T3CM1
T3CM2
T3C
P5CR
VCM
Interrupt Mask
Bit
P52M1, P52M2
P53M1, P53M2
T1IM
SIM
T2IM
T3IM1
T3IM2
T3EIM
P50M1, P50M2
P51M1, P51M2
VIM
Interrupt Source
Any edge at BP52
any edge at BP53
Timer 1
SSI buffer full/empty or BP40/BP43 interrupt
Timer 2 compare match/overflow
Timer 3 compare register 1 match
Timer 3 compare register 2 match
Timer 3 edge event occurs (T3I)
Any edge at BP50,
any edge at BP51
External/internal voltage monitoring
16.8
Software Interrupts
The programmer can generate interrupts by using the software interrupt instruction (SWI), which
is supported in qFORTH by predefined macros named SWI0...SWI7. The software triggered
interrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes the
top two elements from the expression stack and writes the corresponding bits via the I/O bus to
the interrupt pending register. Therefore, by using the SWI instruction, interrupts can be re-prior-
itized or lower priority processes scheduled for later execution.
16.9
Hardware Interrupts
In the microcontroller block, there are eleven hardware interrupt sources with seven different lev-
els. Each source can be masked individually by mask bits in the corres-ponding control
registers. An overview of the possible hardware configurations is shown in Table 16-2.
22 ATAR862-8
4589H–4BMCU–06/07